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Elixir M2Y1GH64TU8HD6B-AC Datenblatt Seite 10

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Seitenansicht 9
M2Y51H64TU88D0B / M2Y51H64TU88D6B / M2Y1GH64TU8HD0B / M2Y1GH64TU8HD6B
512MB: 64M x 64 / 1GB: 128M x 64
Unbuffered DDR2 SDRAM DIMM Preliminary Edition
REV 0.1 10
08/2008
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Serial Presence Detect – Part 2 of 2 (1GB)
128Mx64 2 RANKs UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD
Byte
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
Note
-3C
-AC
-3C
-AC
40
Extension of Byte 41 t
RC
and Byte 42 t
RFC
00: The number below a decimal point
of tRC and tRFC are 0, tRFC is less
than 256ns. 30: The number below a
decimal point of tRC is 5, tRFC is less
than 256ns
06
36
41
Minimum Core Cycle Time (t
RC
)
60.ns
57.7ns
3C
39
42
Min. Auto Refresh Command Cycle Time (t
RFC
)
127.5ns
7F
43
Maximum Clock Cycle Time (t
CK
)
8.0ns
80
44
Max. DQS-DQ Skew Factor (t
DQS
)
0.24ns
0.2
18
14
45
Read Data Hold Skew Factor (t
QHS
)
0.34ns
0.30
22
1E
46
PLL Relock Time
Undefined
00
47
Tcasemax, DT4R4W Delta
Undefined
00
48
Thermal Resistance of DRAM Package from Top (Case) to
Ambient (Psi T-A DRAM)
Undefined
00
49
DRAM Case Temperature Rise from Ambient due to
Activate-Precharge/Mode Bits (DT0/Mode Bits)
Undefined
00
50
DRAM Case Temperature Rise from Ambient due to
Precharge/Quiet Standby (DT2N/DT2Q)
Undefined
00
51
DRAM Case Temperature Rise from Ambient due to
precharge Power-Down (DT2P)
Undefined
00
52
DRAM Case Temperature Rise from Ambient due to Active
Standby (DT3N)
Undefined
00
53
DRAM Case Temperature Rise from Ambient due to Active
Power-Down with Fast PDN Exit (DT3P fast)
Undefined
00
54
DRAM Case Temperature Rise from Ambient due to Active
Power-Down with Slow PDN Exit (DT3P slow)
Undefined
00
55
DRAM Case Temperature Rise from Ambient due to Page
Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W
Mode Bit)
Undefined
00
56
DRAM Case Temperature Rise from Ambient due to Burst
Refresh (DT5B)
Undefined
00
57
DRAM Case Temperature Rise from Ambient due to Bank
Interleave Reads with Auto-Precharge (DT7)
Undefined
00
58
Thermal Resistance of PLL Package from Top (Case) to
Ambient (Psi T-A PLL)
Undefined
00
59
Thermal Resistance of Register Package from Top (Case)
to Ambient (Psi T-A Register)
Undefined
00
60
PLL Case Temperature Rise from Ambient due to PLL
Active (DT PLL Active)
Undefined
00
61
Resister Case Temperature Rise from Ambient due to
Register Active/Mode Bit (DT Register Active/Mode Bit)
Undefined
00
62
SPD Revision
1.3
13
63
Checksum for Byte 0-62
Checksum data
93
79
64-71
Manufacture’s JEDEC ID Code
NANYA
7F7F7F0B00000000
72-255
Reserved
Undefined
--
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